Typically in the interconnection of semiconductor devices, a first layer of insulating dielectric is deposited over previously deposited and/or patterned polysilicon polycide or refractory metal transistor gates, sources, and drains, as well as over previously deposited and patterned capacitor electrodes. Contact holes are dry etched in the insulating dielectric to reach transistor gates, sources and drains as well as capacitor electrodes and any other electrodes that need to be connected to other devices.
A first level of interconnect material is deposited so as to electrically contact transistor gates, sources and drains as well as capacitor electrodes. This first level of interconnect material is dry etched, typically in various chlorine and fluorine containing discharges, using standard photolithography techniques to form interconnect tracks. A second layer of insulating dielectric is deposited over the patterned interconnect material to ensure its electrical isolation. Via holes are dry etched in that insulating dielectric to reach the tracks of the first level of interconnect material. A second level of interconnect material is deposited. The second level of interconnect material is dry etched in a manner similar to the first level. The above steps are repeated many times if more than two levels of interconnect material are needed. Finally a top protective layer is deposited.
The second step of the above sequence, called contact hole dry etching, requires the patterning of small diameter contact holes, in the order of 1.0 .mu.m of diameter, in the insulating dielectric. These contact holes electrically connect the first level interconnect material to transistor polysilicon or silicide gates, to substrate or silicide sources and drains as well as to polysilicon or silicide capacitor electrodes and any other electrodes that need to be connected to other devices.
The sixth step of the above sequence, called via hole dry etching, necessitates the patterning of similarly small diameter via holes, in the order of 1.0 .mu.m of diameter, in the insulating dielectric. These via holes electrically connect the second level interconnect material to first level interconnects.
The insulating dielectric is also dry etched in the scribe lines at each one of these two steps. These scribe lines are large areas, in the order 100.0 .mu.m of width, that are used to permit a diamond saw to physically cut the substrate and form many individual dies from a wafer. Scribe line etching is performed down to the substrate at the second, fourth, sixth and eighth steps.
The point in time when the substrate is reached in the scribe lines is called the end-point. The excess time added to the end-point is called the over-etch time and is used in order to ensure etch completion everywhere on the wafer. This over-etch time must be minimized during contact hole etching because a catastrophic over-consumption of substrate or silicide sources and drain regions can occur because the substrate-to-dielectric or silicide-to-dielectric etch selectivity is not infinite. This catastrophic over-consumption of substrate or silicide regions results in junction leakage and defective devices.
To avoid this catastrophic over-consumption, an automatic etch end-point is used. This automatic end-point is triggered when substantial part of scribe-lines becomes exposed. The sensitivity of most end-point detectors is not capable of detecting the exposure of contact and via holes.
Contact and via hole patterning requires many steps:
a) A positive or negative photoresist solution is spun over the dielectric material to be patterned in order to obtain the desired thickness.
b) The positive or negative photoresist is soft-baked to low temperatures, typically around 110.degree. C. for about 6 minutes in order to evaporate solvents and water.
c) The obtained photoactive positive or negative photoresist film is locally exposed by using photomasks and step-and-repeat or projection alignment equipment. This results in local photo-induced chemical reaction in the positive or negative photoresist film.
d) A developer solution is used to locally remove the areas of the positive photoresist at which photo-induced chemical reactions occurred. The developer solution is used to remove unexposed regions of negative photoresist. The mask pattern is then transferred to the positive photoresist while its reverse image is transferred when negative photoresist is used.
e) The positive or negative photoresist is hard-baked to about 120.degree. C. for about 6 minutes in order to stabilized the obtained pattern and make it suitable for underlying dielectric film dry patterning.
f) The wafer is transferred to a dry etcher. Most dry etchers use glow discharge in various configurations in order to ionize gas mixtures and provoke reactive sputtering and/or formation of volatile gases from the dielectric material to be patterned. Photoresist is used as local mask that prevents etching of underlayer dielectric material, thus transferring the photoresist pattern to the dielectric film.
As an example, typical gas mixtures for dry etching silicon dioxide based dielectric materials include:
An etch gas such as SF.sub.6, CF.sub.4, C.sub.2 F.sub.6, or another fluorine-containing gas that can form volatile silicon-fluorine compounds, PA1 A catalyst gas such as O.sub.2, or He that increases the etch rate by increasing the formation of atomic fluorine from the etch gas. PA1 A passivation gas such as CHF.sub.3, or another hydrocarbon, that permits passivation of the sidewalls and gives some anisotropy. This third type of gas is not necessary if the substrate temperature is maintained very low in order to create an artificial anisotropy by reducing the desorption rate of volatile etch by-products from vertical surfaces while ion bombardment on horizontal surfaces keeps the local etch rate high. PA1 The etch rate of the dielectric will be strongly affected by the surface coverage ratio by the photoresist. This means that the same etch recipe will have different etch rates on different photoresist patterns. As a consequence, smaller devices, associated with a larger total surface of scribe lines not covered by photoresist, will see their dielectric etch rate reduced while the dielectrics of larger devices will etch faster; an effect called the macro-loading effect. PA1 The etch rate of the dielectric, within a mean-free-path distance from a photoresist edge, will not be the same as the equivalent etch rate, far from photoresist areas. Since the mean-free-path, in most gases, is about 1.0 to 3.0 .mu.m at a total pressure of about 5.0 Torr, then the etch rate of small diameter and isolated contact holes in the dielectric will be faster than the equivalent etch rate in scribe lines. The end-point signal will then be ineffective since the scribe lines will begin to clear well after the bottom of contact holes is reached. This may result in catastrophic substrate, polysilicon or silicide over-consumption and in associated junction or capacitor leakage. This effect is also called the micro-loading effect. PA1 The dielectric overall etch rate uniformity and reproducibility will become a steep function of the photoresist baking uniformity and reproducibility. PA1 Any attempt to optimize the dielectric etch module by modifying the etch recipe itself will give very limited effect since the photoresist by-products have a dominant role. PA1 Any search for an improved and capable equipment for the dielectric etch module will probably give disappointing results.
The dry-etch is terminated after a certain over-etch time is added to end-point. The scribe lines are etched-down to the substrate while, in case of the second step, the contact holes are etched down to the transistor polysilicon or silicide gates, to substrate or silicide sources and drains as well as to capacitor electrodes and any other electrodes that need to be connected to other devices. In case of the sixth step, the via holes are etched down to the first level interconnect patterns.
g) The wafer is transferred to a dry photoresist stripper where the remaining photoresist is removed.
h) The exposure of the photoresist to dry etch chemistries, at step f), very often causes dry stripping problems, at step g). For this reason a wet photoresist stripper solution is normally used after step g) to prevent photoresist residues. The wafer is then ready for interconnect material deposition.
Photoresist is a quasi-inorganic material containing carbon, hydrogen, oxygen, nitrogen, silicon and sulphur atoms, among others, that are bonded in such a way as to obtain desirable optical, chemical, physical, as well as mechanical properties. The exposure of this material to different plasma chemistries can cause anomalies within the plasma that can affect global as well as microscopic scale etch characteristics of the dielectric to pattern. The etch rate of the dielectric to be patterned, the etch selectivity of the dielectric and the material present at the bottom of the contacts or via holes, the etch uniformity of the dielectric to be patterned, and the loading effect of the resist during dielectric etch are four of the most important etch characteristics.
A dielectric etch module must be, as far as possible, independent of upstream and downstream process modules and should be, as far as possible, unaffected by variations of these upstream and downstream process modules.
As an example, the etch rate of the dielectric to pattern should be solely a function of the material to pattern and of the etch chemistry.
For a given material, dielectric etch module optimization should be possible by varying the etch parameters according to experimental techniques such as TAGUCHI orthogonal matrices. The parameters of this dielectric etch module to vary can be: power density, total pressure, gas residence time, gas ratios, plasma impedance and ion bombardment, gas type, wafer temperature, etc.
The independence of this dielectric etch module is possible if, and only if, the photoresist pattern module plays a minor role in the optimization of the dielectric etch module. If this is not the case, small fluctuations in the photoresist pattern module may cause major stability effects in the dielectric etch module and out-of-control situations.
As an example of the non-independence of process modules, it will be apparent that the patterned photoresist can be easily attacked by the plasma and can produce large amounts of by-product, such as oxygen atoms that can be used as catalyst, in some conditions, the etch of some dielectrics by more efficiently forming fluorine atoms from fluorine-containing compound etchant, and fluorine compound volatile, from the dielectric to pattern, then: